A switching power-supply device provided in a digital home electrical appliance such as television, recorder and the like is required to have low power consumption at the time of a light load such as remote control standby state. With respect to the demand for the low power consumption, in general, a time period for which driving of a switching element is prevented at the time of the light load is periodically provided to reduce switching loss and to implement the low power consumption (for example, refer to U.S. Pat. No. 5,481,178).
FIG. 5 illustrates an example of a configuration of a switching power-supply circuit according to the background art.
A switching power-supply circuit shown in FIG. 5 has an error amplifier 1, a feedback resistance 2, a switching control circuit 3, a switching operation control circuit 4b, a drive regulator circuit (DRVREG) 5, a diode 6, a bootstrap (BS) capacitor 7, an N-channel type MOSFET 8 serving as a main switching element, a driving circuit 9 driving the MOSFET 8, a current detection circuit 10, an inductor 13 and a capacitor 14 for voltage shaping, a freewheel diode 15, a regulator circuit (REG) 17 and a bias circuit 18b. 
A drain terminal of the MOSFET 8 is connected to a power-supply 19 that supplies a power-supply voltage Vi. A gate terminal of the MOSFET 8 is connected to an output terminal of the driving circuit 9. A source terminal of the MOSFET 8 is connected to a terminal SW that is connected to one end of the bootstrap capacitor 7.
One of two power-supply terminals of the driving circuit 9 is connected to the terminal SW. The other of two power-supply terminals of the driving circuit 9 is connected to a terminal BS that is connected to the other end of the bootstrap capacitor 7.
The terminal BS is connected with a cathode of the diode 6. An anode of the diode 6 is connected with the drive regulator circuit 5.
The terminal SW is connected with a left end of the inductor 13. A right end of the inductor 13 is connected to an output terminal OT of the switching power-supply device.
The capacitor 14 and the feedback resistance 2 are connected between the output terminal OT and a ground, respectively.
A cathode of the freewheel diode 15 is connected between the left end of the inductor 13 and the source terminal of the MOSFET 8 and an anode of the freewheel diode 15 is connected to the ground.
The inductor 13 and the capacitor 14 configure a smoothing circuit, smooth a square wave voltage, which is generated by switching the MOSFET 8, and supply a direct current output voltage Vo to an output load circuit 16 connected to the output terminal OT.
The current detection circuit 10 detects a drain current iD that flows to the drain terminal of the MOSFET 8.
The drive regulator circuit 5 charges the bootstrap capacitor 7 through the diode 6, while the MOSFET 8 is switched from an on-state to an off-state and a regenerative current of the inductor 13 flows to the freewheel diode 15 (during the regenerative time period).
The bootstrap capacitor 7 feeds power to the driving circuit 9 while the MOSFET 8 is in the on-state.
The feedback resistance 2 is to detect the output voltage Vo that is output from the output terminal OT and is configured by two resistances connected in series between the output terminal OT and the ground. An input terminal of the error amplifier 1 is connected between the two resistances.
The error amplifier 1 has a differential amplifier circuit 11, a phase compensation circuit 12 and a power-supply that supplies a preset reference voltage VREF.
The error amplifier 1 generates an error amplification signal Vcomp that is obtained by amplifying a difference between the output voltage Vo detected through the feedback resistance 2 and the reference voltage VREF and outputs the error amplification signal Vcomp.
The switching control circuit 3 has an oscillator 31, a PWM latch 32, a PWM comparator 33, a resistance 34 and an AND circuit 36.
The oscillator 31 generates a pulse signal having constant period and pulse width and inputs the pulse signal to a set terminal S of the PWM latch 32.
The PWM comparator 33 compares a voltage signal Vtrip, which is obtained by current-voltage converting the drain current iD detected by the current detection circuit 10 by the resistance 34, and the error amplification signal Vcomp, which is output from the error amplifier 1, and outputs a signal according to a comparison result to a reset terminal R of the PWM latch 32.
Specifically, the PWM comparator 33 sets an output signal to be a high level when the voltage signal Vtrip is the error amplification signal Vcomp or larger. Also, the PWM comparator 33 sets an output signal to be a low level when the voltage signal Vtrip is smaller than the error amplification signal Vcomp.
When a high-level signal is input to the set terminal S, the PWM latch 32 sets an output signal to be a high level. The PWM latch 32 returns the output signal to a low level at the time that a high-level signal is input to the reset terminal R.
The switching operation control circuit 4b has a power-supply 41 that supplies a voltage of a threshold value VTH1 and a comparator 42.
The comparator 42 compares the error amplification signal Vcomp, which is output from the error amplifier 1, and the threshold value VTH1 and outputs a signal relating to a comparison result. Specifically, the comparator 42 sets an output signal (Light_Load) to be a high level when the error amplification signal Vcomp is below the threshold value VTH1. When the error amplification signal Vcomp is the threshold value VTH1 or larger, the comparator 42 sets the output signal (Light_Load) to be a low level.
The AND circuit 36 of the switching control circuit 3 is input with the output signal of the PWM latch 32 and a signal that is obtained by inverting the output signal of the comparator 42. When both the two input signals are the high-level, the AND circuit 36 controls the main switching element 8 to be the on-state via the driving circuit 9. When at least one of the two input signals is the low level, the AND circuit 36 controls the main switching element 8 to be the off-state via the driving circuit 9.
The regulator circuit (REG) 7 generates a regulator voltage VREG from the power-supply voltage Vi and supplies the regulator voltage VREG to the bias circuit 18b. 
The bias circuit 18b is configured by a constant current circuit 180b in which a plurality of (six, in the example of FIG. 5) constant current sources is connected in parallel. The seven constant current sources generate bias currents i1, i2, i4, i5, i6, i7 from the regulator voltage VREG.
The bias current i1 is supplied to the comparator 42. The bias current i2 is supplied to the error amplifier circuit 11. The bias current i4 is supplied to the PWM comparator 33. The bias current i5 is supplied to the oscillator 31. The bias current i6 is supplied to the drive regulator circuit 5. The bias current i7 is supplied to the current detection circuit 10.
In the below, operations of the switching power-supply circuit shown in FIG. 5 are described with reference to a timing chart shown in FIG. 6.
In FIG. 6, “io” indicates a current that flows to the output load circuit 16. “SW” indicates a voltage of the terminal SW. “voltage between BS-SW” indicates a voltage (voltage between both ends of the bootstrap capacitor 7) between the terminal BS and the terminal SW. “icc” indicates a circuit current that flows to the regulator circuit 17.
At the start time of the operation, since the output voltage Vo=0 and the MOSFET 8 is in the off-state, the error amplification signal Vcomp becomes larger than the voltage signal Vtrip. Accordingly, the output of the PWM comparator 33 becomes a low level. The PWM latch 32 sets the output to be a high level when a high-level signal is input from the oscillator 31. Also, since the error amplification signal Vcomp is sufficiently larger than the threshold value VTH1, the output Light_Load of the comparator 42 becomes also a low level. That is, both two signals that are input to the AND circuit 36 are the high level and the MOSFET 8 becomes the on-state.
When the MOSFET 8 becomes the on-state, the drain current iD increases and the output voltage Vo rises. Accordingly, at certain timing, the voltage signal Vtrip reaches the same value as the error amplification signal Vcomp, the output signal of the PWM comparator 33 becomes a high level and the PWM latch 32 is reset. Thereby, the output of the AND circuit 36 becomes a low level and the MOSFET 8 becomes the off-state. When the MOSFET 8 becomes the off-state, since the drain current iD decreases, the output of the PWM comparator 33 becomes a low level. At this state, when a high-level signal is input to the PWM latch 32 from the oscillator 31, the output of the AND circuit 36 becomes a high level and the MOSFET 8 becomes again the on-state.
At a heavy load state where the output load current io flowing to the output load circuit 16 is high, the threshold value VTH1 is set so that the error amplification signal Vcomp is not smaller than the threshold value VTH1. Therefore, the output signal Light_Load becomes consistently a low level at the heavy load state. Accordingly, at the heavy load state, the switching control circuit 3 performs switching control of alternately switching the MOSFET 8 to the on-state and the off-state and determines time for which the MOSFET 8 becomes the on-state in accordance with the error amplification signal Vcomp.
On the other hand, when the output load current io decreases, the error amplification signal Vcomp starts to decrease, as shown in FIG. 6. As a result, the time period from when the MOSFET 8 becomes the on-state to when the voltage signal Vtrip reaches the level of the error amplification signal Vcomp is gradually shortened. Accordingly, the on-state time of the MOSFET 8 in the switching control is also shortened.
When the error amplification signal Vcomp becomes smaller than the threshold value VTH1, the output signal Light_Load becomes a high level, the output of the AND circuit 36 becomes a low level and the MOSFET 8 becomes the off-state. Thereby, the driving (switching control) of the MOSFET 8 by the switching control circuit 3 is prohibited.
When the output voltage Vo somewhat decreases after the driving of the MOSFET 8 is prohibited, the error amplification signal Vcomp turns to the increase, and when the error amplification signal Vcomp reaches the threshold value VTH1, the output signal Light_Load is switched to a low level. Thereby, the driving of the MOSFET 8 by the switching control circuit 3 is permitted. That is, the MOSFET 8 becomes the on-state at timing at which a high-level signal is input to the PWM latch 32 from the oscillator 31, and then the MOSFET 8 becomes the off-state at timing at which the levels of the error amplification signal Vcomp and the voltage signal Vtrip are the same.
When the driving of the MOSFET 8 is permitted and thus the MOSFET 8 becomes the on-state, the output voltage Vo slightly increases. After that, when the MOSFET 8 becomes the off-state, the output voltage Vo starts to decrease. As the output voltage Vo decreases, the error amplification signal Vcomp again starts to decrease. Then, when the error amplification signal Vcomp becomes again smaller than the threshold value VTH1, the output signal Light_Load becomes a high level and the driving of the MOSFET 8 by the switching control circuit 3 is again stopped.
Like this, at a light load state where the output load current io is small, the time period during which the driving of the MOSFET 8 is permitted, and the time period during which the driving of the MOSFET 8 is prohibited alternately repeat.
As the output load current io is smaller, the decrease of the output voltage Vo during the off-state of the MOSFET 8 becomes gentler. That is, as the load is lighter, the time period from when the error amplification signal Vcomp is smaller than the threshold value VTH1 to when the error amplification signal Vcomp again returns to the threshold value VTH1 becomes longer and the time period during which the driving of the MOSFET 8 is prohibited is prolonged. As a result, it is possible to reduce the switching loss to thus implement the low power consumption.